In integrated circuit design, a through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSVs are a high performance technique currently used to create 3D packages and 3D integrated circuits, compared to alternatives such as package-on-package, because the density of the vias is substantially higher, and because the length of the connections is shorter.
A three dimensional integration (3DI) package contains two or more chips (integrated circuits) stacked vertically so that they occupy less space and/or have greater connectivity. An alternate type of 3D package can be found, for example, in IBM's Silicon Carrier Packaging Technology, where ICs are not stacked but a carrier substrate containing TSVs is used to connect multiple ICs together in a package. In most 3D packages, the stacked chips are wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking).
An example priori art 3D integrated circuit is shown in FIG. 1. The integrated circuit, generally referenced 70, is constructed by stacking multiple silicon wafers and/or dies 72 and interconnecting them vertically so that they behave as a single device. By using TSV technology, 3D ICs can pack a great deal of functionality into a small “footprint.” The different dice in the stack may be heterogeneous, e.g., combining CMOS logic, DRAM and III-V materials into a single IC. In addition, critical electrical paths through the device can be drastically shortened, leading to faster operation.
Improvements in IC technology are leading to continued increases in IC operating speeds. For example, recent technology offers a tremendous increase in on-chip signal bandwidth in the areas of analog and mixed signal (AMS) design, providing operating speeds in the region of tens of Gigahertz. As operating speeds reach the multi-Gigahertz range, on-chip interconnect lines and TSVs, i.e. wires connecting circuit components on the same or different chip levels, can have a major impact on IC performance. High speed design is characterized by a frequent need for true-transient time-domain simulations, high importance of signal integrity, and characteristic bandwidths in the microwave region. Thus a consideration of on-chip interconnect line and TSV effects becomes necessary. Moreover, early incorporation of interconnects and TSVs in the design process is highly desirable because a traditional post-layout treatment of on-chip interconnects and TSVs can lead to numerous design iterations or a significant amount of over-design.
The three-dimensional integration (3DI) chip technology concept offers a potential for improving systems performance in addition to the planar technology scaling, which is now experiencing a considerable drop in performance improvement per node.
Building viable systems of stacked chips with very high density vertical interconnections is impossible without means which enable precise prediction of the expected 3DI circuitry behavior. Preferably, the solution should model both horizontal and vertical interconnects with high accuracy for both AMS and digital design in an actual design environment, including silicon substrate, surrounding vertical and horizontal interconnect, etc. In addition, it should be simple to operate, fast, consider technology specifics (e.g., BEOL, FEOL, inter-strata dielectric structure, etc.), support different simulation both in time and frequency domain, and be fully integrated within common design flows and environments.